Single-crystal silicon carbide has a band gap and a critical electric field strength that significantly exceed that of single-crystal silicon. Therefore, single-crystal silicon carbide replaces the current mainstream insulated gate bipolar transistors (IGBTs) of high voltage semiconductor devices with transistors such as metal oxide semiconductor field effect transistors (IGFETs) and bipolar junction transistors (BJTs) for which loss is lower than for IGBTs; or is expected to be a semiconductor material that can realize an ultra-high voltage semiconductor device for voltage exceeding 10 kV as a single device. In the process for fabricating the silicon carbide semiconductor device, when an ohmic contact is formed, the simplest manner is to deposit a thin metal film on a single-crystal silicon carbide substrate, and to apply thereto heat annealing at about 1,000 degrees C. in an inert gas such as argon (Ar). At present, the material of the metal thin film used to form the ohmic contact is generally a nickel (Ni)-based metal.
In a vertical semiconductor device, electric current has to flow in the back face of the substrate and therefore, one of the most important tasks is to reduce the contact resistance between the back face of the substrate and a back face metal. As a solution, the dopant concentration in the back face of the substrate may be increased, or the effective area of the back face of the substrate can be increased by intentionally roughing the back face. In particular, the latter can be realized using relatively simple processing such as grinding and therefore, it is estimated that this method is advantageous for the fabrication of the semiconductor device.
Nonetheless, the single-crystal silicon carbide substrate is typically a highly fragile material and therefore, when machine work is applied to the back face after fabricating the device structure on the front face, pressure may locally concentrate and this may lead to cracking and chipping of the substrate. In contrast, when the back face of the substrate is roughened by grinding, etc., in the early stage of the overall fabrication process before the fabrication of the device structure on the front face, dust tends to be generated when the substrate is conveyed at this process step and thereafter and therefore, the yield may be reduced especially for a device that needs to have fine structures such as transistors fabricated therein.
It is known especially for the MOSFET among the types of transistor that the device properties such as the mobility can significantly be improved by terminating using a hydrogen atom a dangling bond of a silicon atom present in the interface between the gate oxide film and the silicon carbide. To avoid breaking this hydrogen terminal, it is important to lower the temperature as much as possible of the process steps to form the gate electrode and those thereafter. On the other hand, a higher annealing temperature is more advantageous for reducing the contact resistance of the back face metal on the back face of the substrate and therefore, a solution is necessary for these conflicting requirements to fabricate the MOSFET.    Patent Document 1: Japanese Laid-open Publication No. 2006-32458    Patent Document 2: Japanese Laid-open Publication No. 2006-41248    Non-patent Literature 1: Saji, et al, Research Conference Documents of The Institute of Electrical Engineers of Japan, Electronic Device Material Conference, EFM-90-20, 1990.    Non-Patent Literature 2: Toshiba Review, Vol. 63, No. 10, p. 39 (2008).